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- The tool converts raw information in the form of a
word document into synthesizable VHDL modules
- The tool is generic i.e it can generate VHDL codes for
any GCI between any microprocessor and any Core except that the format in which the
engineer specifies the data is the same.
- The automatic customization of the GCI helps to save
valuable design time since it avoids the cumbersome task of manually coding individual
register entities
- The number of registers and register banks are
scalable i.e there can be any number of registers and banks, the only limitation being the
memory of the system.
- It provides simple to use word macros to parse the
word file because it becomes simple to access any text file in languages like JAVA/C++ etc
- It provides a comprehensive error check for the word
document file given in at the user end.
- Errorless VHDL modules are generated for all the
registers specified in the table.
- It provides an easy to use interface at the front end
- It has user feasibility in the form of Help Files,
which give the user a complete guide as to how to use the product.
- Since it is designed in Java the tool is robust and it
can run on any platform like Windows9x/Windows2000/WinNT, Linux,Unix (AIX) etc.
- The buttons and panels provided on the front-end
appeal to the aesthetic sense, are self-explanatory and guide the user to use the product.
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