Integrated circuit technology in the past few years has been pervasive and has had an
imbibing influence in fields ranging from consumer products to business management. The
era of technical development pertaining to this task encompasses a very large scale
integration of micro-electronic circuitry (VLSI). The VLSI deep sub-micron technology
shrinks below 0.2 micron and more lithography levels are substantiated at finer dimensions
(up to 15 in a VLSI chip). This sub-microelectronics era is characterized by ability to
provide large and diverse functions on an individual integrated circuit and by the need
for innovative and aggressive design. Hence the driving force behind the pervasiveness is
unquestionably the exponential increase in scope and complexity of the functional
capability of the modern IC. The ubiquitous need for automation and user feasibility
exhorts technocrats to provide pellucid and tangible products to the electronic market.
Today’s complex IC’s are made up of re-usable pre-verified blocks called
CoreCells. Each CoreCell provides for the microprocessor access to its internal registers.
Modern technological advances have standardized this microprocessor interface by the
design of a Generic Control Interface Block (GCI) . The GCI is a hardware interface
between the microprocessor signals and the CoreCell of a chip, its basic function being
the conversion of the microprocessor signals into a format decipherable to the CoreCell
and hence the GCI forms an integral part of the CoreCell. Its flexible and scalable
architecture allows for easy design, with different numbers of registers, for different
CoreCells/Chips.
The customization of the GCI for different CoreCells/Chips is
laborious and cumbersome due to the presence of large number of registers and manual
coding of these modules. This necessitates the use of a tool that can perform this
customization automatically and save valuable design time. Apropos this necessity, our
project caters to the need for automation in chip design and hence provides a tool to
automate the Generic Control Interface (GCI) in a VLSI chip. This smart tool will
automatically use the microprocessor signals in a hardware description language (VHDL: in
this regard) and generate a gate level net-list for the registers in the CoreCell to
decipher and function accordingly. The proposed tool will read the CoreCell/Chip register
information from a word document. This information along with the GCI architecture will be
used to generate the customized GCI.
This project also describes the implementation of design
structure, rules and associated checking procedures to ensure manufacturability of the
tool. Computational resource constraints are taken cognizance of and algorithmic
tradeoffs, an inseparable part of application programming, are considered. It induces
apposite engineering judgments to forsake some design flexibility to improve the
efficiency of the task relegated to the design system. The basic function of this tool
will be to read a word document and generate the VHDL entities for the registers in it.
The format of the word document will be flexible. Hence the project also entails an
in-depth knowledge of the VHDL language, it’s syntax and semantics.
A major part of the tool building incorporates
programming in Java2, by which information procured from the document will be stored in a
structure. The document is read by using user-defined macros in MS Word, inherited by
Visual Basic Scripts. The second and most important part would be to read this structure
and convert the relevant information into VHDL coded entities and store them into a file.
The code written should be precise enough to be verified on any VHDL simulator like
Xilinx, Synopsis etc. Finally as all designs should cater for testability and should be
functionally verified, this tool will also create a Test Bench that will verify the
customized GCI generated. The front end (GUI) of the tool will primarily be designed using
JFC Swing and the Back-End will be done in Java2 application programming.
Features of the Auto GCI Tool:
GUI
Read the word document for register information.
Create the VHDL modules.
Generate the Test Bench.
Create the GCI Design Doc
Flexible Architecture to incorporate future GCI Architecture changes.
An underlying theme present throughout our project is the
need to address economic constraints with an emphasis on designer productivity and utmost
reliability. Finally our main aim is to put forth a product developed with a minimum
amount development cost to keep in terms with the fast-changing economic market.
